Universal OSI RAM Board Project

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glitch
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Universal OSI RAM Board Project

Post by glitch » Mon Mar 06, 2017 2:35 pm

This is the production board that resulted from:

32/64KB 8-bit RAM: http://www.osiweb.org/osiforum/viewtopic.php?f=3&t=297
12-bit RAM with lamp register: http://www.osiweb.org/osiforum/viewtopi ... 330&p=2096

I'm laying it out in KiCad from the prototypes that I built. It's got sockets for 128 KW x 12 bits of 62256 SRAM. It'll work with Ferroelectric RAM too, I'm not sure if I will put write lockout onboard or just build it in prototype area -- would other people like to use FeRAM? It's basically core on silicon, completely nonvolatile, no batteries, effectively no write limit. It's wide voltage so you have to lock out writes and/or hold the CPU in reset until power stabilizes, something that the OSI doesn't have by default but can be built in to the RAM board. There's also a /RESET line that can be driven on the bus.

Like the prototypes, you can enable/disable RAM in 4K blocks, so if you have ROM or existing RAM you want to use, you can just make a hole for it. There's no memory management circuitry on board, but the segment decoders have spare inputs intended for memory management. Is this something that people would like laid out on the board? There's a ton of spare room, as you can see from the below gerbv rendering. I figure most people won't need banked RAM, but having it onboard makes it easy to expand, plus with the 4K segment select you can do things like have both 64K banks mapped onto bank 0, and put a ROM in one of them, and selectively enable 4K pages of ROM.

There's a big chunk of prototype area, I'll probably bring the address and data busses out to the edge of it and put in a labeled array of pads. Probably a single or dual row pin header so you can solder to the holes or put a header in and wire wrap. The circuitry that controls the bus drivers has spare inputs that are pulled up with resistors so that you don't have to lay out new bus transceivers. You can also drive the memory management inputs on the decode logic to insert devices into otherwise contiguous memory space.

Bus buffering is with 74LS241 octal inverting bus buffers, so no depending on hard to source vintage ICs. You can still swap them out with a 74LS240 and get a noninverting bus, if that's what your OSI uses.

Here's a capture from gerbv:

Image
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glitch
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Re: Universal OSI RAM Board Project

Post by glitch » Tue Mar 07, 2017 3:56 pm

Decided to add memory management in copper after discussing it on IRC. It'll be disableable by simply omitting the ICs, or adding a pull-down resistor if you populate it then decide you don't want it.

Adding a header for a lamp register mezzanine next -- I figure I'll do it as a small mezzanine board so that the lamps can be grouped in hex or octal, depending on the application. It'll also allow mezzanine boards with hex or octal displays (like the TIL311). I'm bringing up A0, *RD, and *WR on the connector, so if you don't use the lamp register, there's a convenient completely decoded set of control lines to use in the prototype area. Mezzanine connector and standoffs will be on 0.1" centers so you can do your own thing with a piece of perfboard, too.

Using a mezzanine also means you can easily connect it with a ribbon cable and mount it to the front of an enclosure or something. Or at least turn it around so you can see it if it's on the 560Z SYS bus and essentially facing backwards!
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MK14HAK
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Location: New Zealand

Re: Universal OSI RAM Board Project

Post by MK14HAK » Tue Mar 07, 2017 11:14 pm

glitch, Do the 4K page selects cover a full 64K block?
Pleased to see the bank memory management implemented. Will help will those big C compiles !
So these 62256 SRAM sockets are optionally ROM also and can be for Z80 code ?
Thanks for the very helpful website.
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glitch
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Re: Universal OSI RAM Board Project

Post by glitch » Wed Mar 08, 2017 12:34 am

Yep, it can cover 0-64K in 4K blocks. Each 64K bank can be mapped to any extended address segment, if memory management is desired.

It will work with a Z80 on both the 560Z board or on e.g. the 510 triple CPU board. Should support all processors possible to use in an OSI with zero wait states.
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glitch
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Re: Universal OSI RAM Board Project

Post by glitch » Thu Apr 06, 2017 1:56 am

Progress!

Image

Messed around with 3D view mode in KiCad some today, and got things matched up for mostly what it will look like. Pretty sure everything is routed correctly, but I'm going to look through it again tomorrow morning. Should be ordering boards this week!

There's a header in the upper-left quadrant of the board that will be for the lamp register mezzanine. I was going to put it directly on the board but decided it would be nice to have a mezzanine so you can group LEDs in hex or octal. I'll probably do a smart display board for it, too.

The leftover area will be filled with proto space.
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glitch
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Re: Universal OSI RAM Board Project

Post by glitch » Thu Apr 06, 2017 3:50 pm

Had a look over the board, made a few tiny corrections, and re-annotated the resistors and R-packs to be in "correct" order (left to right, top to bottom, as viewed on the board). I added in the mounting holes for the mezzanine board, prototype area, part number and board info, and of course the OSHW logo :) Renderings of bare board and with components:

Image

Image
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dave
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Re: Universal OSI RAM Board Project

Post by dave » Thu Apr 06, 2017 10:35 pm

Very nice!

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glitch
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Re: Universal OSI RAM Board Project

Post by glitch » Thu Apr 06, 2017 10:40 pm

Thanks! I ordered prototypes today, I should be able to offer the bare boards for $25/each as with the OSI 560Z boards. If the prototypes work I'll probably sell them fully populated/tested to recoup some of my prototyping costs.
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Parts bin Challenger 3 board set, never had a chassis in its time

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glitch
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Re: Universal OSI RAM Board Project

Post by glitch » Wed May 03, 2017 11:38 pm

Got a chance to build a lamp register mezzanine today and test the thing fully with the 560Z board. Success! Writeup here:

http://www.glitchwrks.com/2017/05/03/gw ... versal-ram

Picture with prototype octal lamp register installed:

Image
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glitch
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Re: Universal OSI RAM Board Project

Post by glitch » Thu May 04, 2017 3:21 pm

I started laying out the octal lamp register last night, and wrapped it up this morning:

Image

Included a jumper to disable the upper four bits, so the mezzanine can be switched between 8- and 12-bit modes without pulling an IC.
Check out The Glitch Works
OSI Challenger 3, 510 CPU, 8" floppies, 74 MB hard disk system in need of restore
Parts bin Challenger 3 board set, never had a chassis in its time

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