FPGA Implementations

w4jbm
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Joined: Sun Jun 18, 2017 1:41 pm

FPGA Implementations

Post by w4jbm » Sun Jun 18, 2017 2:09 pm

New here, but my first computer was a C1P back in 1980. I later traded it for a C4P MF and ended up working for the local dealer in Tulsa for several years in college (and doing freelance work afterwards). Searching for a C1P and a C3, but that's a different story...

I started with my first FPGA project a few weeks ago using Grant Searle's Multicomp (6502, 6809, or Z80) design. After getting that working I moved on to the UK 101 which was designed for PAL video but that I was able to get working on NTSC without too much trouble.

After that, I spent more time tweaking the video code and the ROM and now have a UK 101 that has 24 characters by 25 line video on NTSC.

Up next is swapping out the UK 101 ROMs with OSI ROMs in the project and hopefully having a fully functional C1P in a $20 FPGA.

I've attached a photo my breadboarded (literally) system. Clockwise from the lower left corner is the FPGA board, 128K of memory, the composite vido out & PS/2 keyboard in jacks, and and RS-232 serial port level converter.
IMG_20170617_133958.jpg
Have run into some interesting and unexpected things that actually have potential. Working on the video, I could not figure out how some stuff was eventually scrolling into view instead of hitting the bit bucket because I only had 1K of video RAM allocated in the FPGA. It turned out that the RAM chip "fills in" any unused portions of the address space. So I was writing some stuff to system RAM and it was scrolling into the video memory as I worked on patching scrolling for the 24x25 video format.

I have taken Grant's OSI BASIC code and have that working with all the bug patches and scrubbed of a few things (like typing A at the reset prompt to get the author's name) to free up some space and change a some other things.

So far I have about $50 invested and half of that is for the JTAG USBblaster used to program the FPGA board. All of the parts were either from Amazon or the junk box. I can clock it at 16.67 MHz in the serial mode and it works flawlessly. (I haven't set up the fast clock in the UK101 code yet.)

The only variance from Grant's instructions have been a small capacitor on the memory board and the use of a pre-built RS-232 level converter (3.3 volts in and RS-232 out). The only problem I've had was that I reversed the data and clock lines on the PS/2 keyboard jack and that was totally me not bothering to check the pinout and making an guess based on how other connectors I've used were pinned.

I was curious if others are tinkering much with FPGAs. I see that some of Grant's work was ported to the MiST board. I'm probably going to move to a more powerful board at some point and the MiST is one I'm considering. Seems like if they have Grant's basic machine running it should be reasonable to get the UK101 running. And if you can do that, evolving it to a C1P or a C2-4P isn't unreasonable.

Thanks,
Jim W4JBM
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Steve Gray
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Location: Markham, Ontario, Canada
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Re: FPGA Implementations

Post by Steve Gray » Mon Jun 19, 2017 1:18 am

Nice. I've visited Grant's pages many times. I purchased the FPGA board he recommends, and a ram chip, but that's about where it ended... someday I'm hoping to try it.. someday ;-) I emailed Grant about expanding it to make it more like a C4P, adding sound etc. So, if you can do that I'd definitely be interested in trying it!

I did take Grant's UK-101 circuit and entered it into KiCad, made a few changes, and designed a PCB, but haven't sent the PCB to get done yet. I'm trying to decide if I want to try it as-is or modify it for some expansion options.

Steve
C4P+D&N floppy not working, 2x C4P not working, C1P not working, Superboard not working.
505 board, 610 board, Mittendorf board, TOSIE hacker board need testing, PicoDOS disk untested

RedskullDC
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Joined: Thu Jul 18, 2013 11:24 am

Re: FPGA Implementations

Post by RedskullDC » Mon Jun 19, 2017 12:42 pm

Hi Jim, Steve, et al.

Good work!

I did port Grant's code across to the Terasic DE0_CV board a couple of years ago.
Added VGA out, and 32KB ram modes.

You can find the files on the OSI FPGA yahoo group at:
https://groups.yahoo.com/neo/groups/osi_fpga/info

Cheers,
Leslie
VK2LR
Superboard II - RevD, 8Kb, DABUG monitor ROM.
FPGA C1P/C2/C4. 1-8MHz, 48Kb ram, CEGMON, 16KB Hires.

Steve Gray
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Location: Markham, Ontario, Canada
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Re: FPGA Implementations

Post by Steve Gray » Mon Jun 19, 2017 4:04 pm

RedskullDC wrote:
Mon Jun 19, 2017 12:42 pm
You can find the files on the OSI FPGA yahoo group at:
https://groups.yahoo.com/neo/groups/osi_fpga/info
Wow, has it been 7 years since my last post there? Gary helped me get his project working on my Nexys2 dev board and then without ability to load anything I guess I lost interest. Have things changed much since then?

Steve
C4P+D&N floppy not working, 2x C4P not working, C1P not working, Superboard not working.
505 board, 610 board, Mittendorf board, TOSIE hacker board need testing, PicoDOS disk untested

RedskullDC
Posts: 40
Joined: Thu Jul 18, 2013 11:24 am

Re: FPGA Implementations

Post by RedskullDC » Tue Jun 20, 2017 11:14 am

Hi Steve, Jim, et al.

Gary seems to be putting a lot of work into his "coco3fpga" project, which has a fair bit of momentum behind it at the moment.

I wouldn't mind adding C2/C4 compatibility modes to the code if people are interested?

Shouldn't be too difficult?
Reverse the keyboard logic levels.
Add emulation of the ACIA, and the different memory locations on the C4.
Add extra screen memory/modes.
Add colour memory.

Anything I missed?

I've spoken to Grant before, and he is happy for any mods to be made to the source and released as long as any code which are based on his originals maintain due reference back to him.

Cheers,
Leslie
Superboard II - RevD, 8Kb, DABUG monitor ROM.
FPGA C1P/C2/C4. 1-8MHz, 48Kb ram, CEGMON, 16KB Hires.

Steve Gray
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Location: Markham, Ontario, Canada
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Re: FPGA Implementations

Post by Steve Gray » Tue Jun 20, 2017 1:32 pm

I'd definitely be interested. It sounds good! I think those changes should do it.

Steve
C4P+D&N floppy not working, 2x C4P not working, C1P not working, Superboard not working.
505 board, 610 board, Mittendorf board, TOSIE hacker board need testing, PicoDOS disk untested

w4jbm
Posts: 23
Joined: Sun Jun 18, 2017 1:41 pm

Re: FPGA Implementations

Post by w4jbm » Wed Jun 28, 2017 1:33 am

There was a D to A converter on the C4P.

The thing I've really pondered is using an SD card and having floppy emulation. I know I don't have the chops to implement that at this point.

But I would love to have a full C4P MF in FPGA.

I've been a member of the yahoo group for years but didn't really understand much until I finally built something.

Thanks,
Jim

RedskullDC
Posts: 40
Joined: Thu Jul 18, 2013 11:24 am

Re: FPGA Implementations

Post by RedskullDC » Wed Jun 28, 2017 3:27 pm

Hi Jim, Steve, et al.
w4jbm wrote:
Wed Jun 28, 2017 1:33 am
...
The thing I've really pondered is using an SD card and having floppy emulation. I know I don't have the chops to implement that at this point.
But I would love to have a full C4P MF in FPGA.
I've been a member of the yahoo group for years but didn't really understand much until I finally built something.
Thanks,Jim
A C2/C4 in a FPGA won't be too far away.

I've been working on it the last few days while the forum has been down.

Already completed:
32KB/48KB main RAM (switch selectable)
64x32 screen mode
Inverted Keyboard logic
Moved the ACIA from $F000 -> $FC00
Cegmon C2 ROM support, with the $FCXX block running at either $F4XX or $F7XX.
4 bit Colour support (3 colour bits + inverse).
Double width 32x32 screen mode, and auto switching.
Switch selectable screen layout between C1 and C2/C4.
Switch selectable character generator (UK101 or OSI).
Load/Save programs to PC via USB<=>TTL serial interface.
XGA (1024x768@60Hz) picture mode to allow full screen usage.
(Horizontal pixels are doubled, and vertical pixels are tripled. 512x256 => 1024x768).

----
Colour isn't quite right on the 32x32 screen mode just yet, colours doesn't line up with the characters.
Probably something simple I've overlooked.

Floppy emulation would be cool. I would need to understand a bit better how OS65D works before attempting that though.

Sample pic:

Image

WIll post all the code to github when it's all working as expected.

Regards,
Leslie

dave
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Re: FPGA Implementations

Post by dave » Wed Jun 28, 2017 3:42 pm

Hi Leslie,

That's awesome. Disk emulation would involve emulating the control register interfaces of the floppy interface ACIA and PIA, and mapping that to an SD-card filesystem. I think an FPGA implentation of a rigid FAT filesystem (say, 1 fixed size file per side/drive) would be straightforward, but a microcontroller might make quicker work of it.

These links contain excellent descriptions of the disk operation:

http://osiweb.org/computes_gazette/Comp ... _Part1.pdf
http://osiweb.org/computes_gazette/Comp ... _Part2.pdf

Can't wait to see whatever you come up with.

Dave

Steve Gray
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Location: Markham, Ontario, Canada
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Re: FPGA Implementations

Post by Steve Gray » Wed Jun 28, 2017 3:51 pm

Very nice!!! Time to get out my fpga dev boards!

Steve

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