FPGA Implementations

stm
Posts: 43
Joined: Mon Oct 27, 2014 10:23 pm
Location: Germany

Re: FPGA Implementations

Post by stm » Sat Jul 01, 2017 1:51 pm

About two years ago I tried to get a floppy emulator project for the Challenger 1P started. The goal was to simulate a 610 board attached to the C1P's expansion connector. I used a Papilio Duo board with 512 kB SRAM.

I started with zero knowledge of VHDL, and it was a lot of fun to learn VHDL, but at the end of the day it was too complex for me. As a first step I wanted to simulate a memory chip attached to 6502 bus, so I could write values to the FPGA's RAM from the C1P and read them back in to verify. I had to give up when I had an implementation for this that apparently worked in the FPGA simulator, but not when I tried to run it on the real hardware. I did not have enough know-how and tools to debug what was going wrong in reality...

Having said that, I would still be very interested to participate in any FPGA project that attempts to simulate the floppy controller and disks attached to the C1P. If anyone wants to work in that direction, I would love to hear about it.

Stephan
C1P Model 600 CPU 1978 REV B, 40K (8K original and 32K BillO memory expansion), RS-232
Maintainer of cc65 OSI target

w4jbm
Posts: 23
Joined: Sun Jun 18, 2017 1:41 pm

Re: FPGA Implementations

Post by w4jbm » Sat Jul 01, 2017 7:57 pm

Thanks for sharing Leslie! I should have the new FPGA board in a week or so. Looking forward to trying this out.

If anyone is interested, I'm happy to share the "work in progress" of a C1P based on Grant Searle's UK101 work. Most of what I have done is modify the video code so it provides a 24 character x 25 line NTSC screen and patch the ROMs to properly support the new screen size. I still want to try the original C1P ROMs instead of the patched UK101 ROMs and will share once that is done.

Stephan--I'm going to start a new thread on floppy emulation and share some thoughts I have. I would love to come up with something workable although I have mixed feelings about whether it would be easiest to do in FPGA or on something like a Raspberry Pi.

Thanks,
Jim

stm
Posts: 43
Joined: Mon Oct 27, 2014 10:23 pm
Location: Germany

Re: FPGA Implementations

Post by stm » Sat Jul 01, 2017 10:16 pm

Hi Jim,
w4jbm wrote:
Sat Jul 01, 2017 7:57 pm
Stephan--I'm going to start a new thread on floppy emulation and share some thoughts I have. I would love to come up with something workable although I have mixed feelings about whether it would be easiest to do in FPGA or on something like a Raspberry Pi.
I didn't want to share all my failures in a single post ;)

My more recent experiments for implementing a floppy emulator were actually performed with a Raspberry Pi Zero attached to the 6502 bus, and that turned out to be difficult as well.

I already saw that you opened another thread about the floppy emulation, and there I will write more about the challenges that I faced.

Stephan
C1P Model 600 CPU 1978 REV B, 40K (8K original and 32K BillO memory expansion), RS-232
Maintainer of cc65 OSI target

w4jbm
Posts: 23
Joined: Sun Jun 18, 2017 1:41 pm

Re: FPGA Implementations

Post by w4jbm » Thu Jul 06, 2017 10:22 pm

Got the DE0-CV board today from Digi-Key today. Used the USB cable that came with it to upload the .SOF file and it booted right up. (Attachments seem to be disabled or I'd upload a picture.)

I have a couple of things I want to give a try. Will probably dig around in the VHDL code a bit to make sure I have some basic understanding of how it is working. For it and the C1P I've been working on I also want to remap the keyboards so the keys batch the marking instead of the original OSI mapping if you want. But I'd like to see if I can get disk BASIC and the editor / assembler running without a disk. (Maybe with a HEX loader or something. I do need to wire up the serial interface.)

I think I need to upgrade my version of Quartus also. I'm running 13.1 because that was the last version to support the Cyclone 2. I could upload the SOF but with a quick look it didn't look like I could compile for the Cyclone V.

But I have to say thanks Leslie--you did an incredible amount of heavy lifting to get it as far as you have as fast as you have.

I also have to say that one thought that keeps crossing my mind is how easy it would be to port the 6809 in instead of the 6502. You would need new firmware throughout, but back in the day I kind of thought of the 6809 as being the logical 16 bit successor to both the 6800 and the 6502. But that's a project to consider if I ever have a few weeks to focus on it. :-)

I'll post any updates (and probably a fair number of questions) as I muddle through.

Thanks again,
Jim

RedskullDC
Posts: 40
Joined: Thu Jul 18, 2013 11:24 am

Re: FPGA Implementations

Post by RedskullDC » Fri Jul 07, 2017 4:48 am

hi Jim, et al.
w4jbm wrote:
Thu Jul 06, 2017 10:22 pm


I have a couple of things I want to give a try. Will probably dig around in the VHDL code a bit to make sure I have some basic understanding of how it is working. For it and the C1P I've been working on I also want to remap the keyboards so the keys batch the marking instead of the original OSI mapping if you want. But I'd like to see if I can get disk BASIC and the editor / assembler running without a disk. (Maybe with a HEX loader or something. I do need to wire up the serial interface.)

I think I need to upgrade my version of Quartus also. I'm running 13.1 because that was the last version to support the Cyclone 2. I could upload the SOF but with a quick look it didn't look like I could compile for the Cyclone V.
....

I also have to say that one thought that keeps crossing my mind is how easy it would be to port the 6809 in instead of the 6502. You would need new firmware throughout, but back in the day I kind of thought of the 6809 as being the logical 16 bit successor to both the 6800 and the 6502. But that's a project to consider if I ever have a few weeks to focus on it. :-)

I'll post any updates (and probably a fair number of questions) as I muddle through.

Thanks again,
Jim
Glad it's working for you.

Keyboard layout is a hassle when emulating most of the old 70s machines.
Can become complicated simulating shift key presses, or hiding the shift for some combinations.

One easy solution is to use a PS/2 keyboard with "Japanese International" [JIS] layout.
They have the old style key combos. Preferably without Kana chars shown.
Search EBay for 91 key, or 108 key keyboards. They can be found fairly cheaply.

I use one of theses for FPGA retro stuff, a Filco FKB91:
http://www.keyboardco.com/keyboard_imag ... _large.jpg

---

Quartus changed their IP stuff a lot from V15 ( I think) onwards.
Well Worth updating to the latest V17 though.
Tip: If you have the memory, keep the project directory in a RAM disk.
Compilation time for me falls from about 3:00 minutes on an SSD to 45 seconds on the RAM disk.

---

6809 is easily done.
Jonathan Kent's 6809 core is freeware, but not cycle exact. Runs a bit fast.
There is a newer 6809 by someone else, but I don't have the details handy.

Is there 6809 firmware for the multi CPU OSI board floating around?

---

Look forward to seeing what ideas you come up with.
If you have looked at the source changes I have made, you can see I'm big on comments.
Look at something 6 months down the track, one can forget the reasons for some of the code choices :roll:

Don't hesitate to ask anything.

Cheers,
Leslie
Superboard II - RevD, 8Kb, DABUG monitor ROM.
FPGA C1P/C2/C4. 1-8MHz, 48Kb ram, CEGMON, 16KB Hires.

w4jbm
Posts: 23
Joined: Sun Jun 18, 2017 1:41 pm

Re: FPGA Implementations

Post by w4jbm » Fri Jul 07, 2017 1:36 pm

I don't know of any 6809 firmware, but I do know that there was some 6800 stuff being used in systems with the 510 board (6502/6800/Z80 processors). Probably most of it (or all of it) is lost in the sands of time. :-(

I haven't seen much mention of the Denver Boards. They included a 6502 processor, ACIA, and 48K of memory all on one board. You could upgrade a multiuser system with several of them so you didn't have to share memory or processor time. I did the upgrade for several clients. They would buy the Denver Boards and I would do the upgrade (install the boards, configure the DIP switches, rewire the serial terminal panel on the back of the computer to the new boards, and patch OS65U) in exchange for the 510 CPU card and the 48K of memory that they didn't need any more. I know I still have some of those around but haven't found the right box yet. But I did later sell one of the 510 cards to a guy who was a 6800 enthusiast.

I believe there was either a pin-for-pin compatible version of the 6809 or an adapter board that let it plug into a 6800 socket. I know some people were talking about modifying the 510 board to support the 6809 and building a new OS around that, but so far as I know that was just hobbyist brainstorming about things that would be cool.

I used to jump around different assembly languages (6502, Z80, and the ModComp mini computers), but I'm not sure I could do that these days. Otherwise I'd start tinkering with some 6809 code. I recently got a Tandy CoCo up and running, so I've looked at the 6809 a bit as it relates to that system.

Thanks,
Jim

RedskullDC
Posts: 40
Joined: Thu Jul 18, 2013 11:24 am

Re: FPGA Implementations

Post by RedskullDC » Sun Jul 09, 2017 1:35 pm

Hi Jim, Steve, Dave, Stephan, et al.

Thought about a few different ideas for the project while on the road last week.

Tonight I started adding a couple of new features:

4 different CPU speeds selectable by 2 slide-switches: 0, 1, 2, 4MHz (though it's possible to go much higher).

Patched the bytes in the CEGMON image to allow full 64x32 (was constrained as 64x28).
16KB "Mittendorf" style HIRES mode memory at $8000-$BFFF. 16KB will allow a 512x256 dot addressable pixel display.

I say "style" because until some documentation surfaces, it's all guesswork.

I'm thinking of using two of the unused bits in $DE00 to:
1. Enable/Disable HIRES mode
2. Enable/Disable mixing normal TEXT mode with the HIRES data. That would allow some cool effects, especially if colour is also mixed in.

I noticed a small bug in the video code too.
Appears to be showing one row too many at the bottom of the screen. Will fix that up.

Still thinking about the whole DISK emulation issue....
There is a big 64MBx16 SDRAM chip going unused there, enough to hold *many* disk images at once.
The images could be auto-loaded from the SD-Card at power-on time.
A button press could initiate saving them back.

Cheers,
Leslie
Superboard II - RevD, 8Kb, DABUG monitor ROM.
FPGA C1P/C2/C4. 1-8MHz, 48Kb ram, CEGMON, 16KB Hires.

RedskullDC
Posts: 40
Joined: Thu Jul 18, 2013 11:24 am

Re: FPGA Implementations

Post by RedskullDC » Mon Jul 10, 2017 1:37 pm

Hi Jim, et al.

New build you may like to try.

Hires may not be your bag, but the speed boosts are cool ;)
----

Important differences:

4 different speed selects:

Controlled by physical switches 1 and 0
SW1 SW0
off off = 1 MHz
off on = 2 MHz
on off = 4 MHz
on on = 8 MHz

Switchable on the fly!

Added 16KB Hires area at $8000-$BFFF or 512x256 dot addressable.
Controlled by:

$DE00 bit 4 : 0 = TEXT, 1 = HIRES ENABLED ( force on with physical switch 2)
$DE00 bit 5 : 0 = HIRES ONLY, 1 = HIRES + TEXT mixed ( force on with physical switch 3)

** Set Memory Size to 32767 so BASIC doesn't clobber the HIRES SCREEN area **

Sample showing some random bytes being written to the second half of the hires area with mixed text/hires enabled:

Image

Code and programming file has been updated to the latest at:
http://www.crisis.com.au/images/OSI_Searle_Q17.zip

I think disk emulation next.....

Cheers,
Leslie
Superboard II - RevD, 8Kb, DABUG monitor ROM.
FPGA C1P/C2/C4. 1-8MHz, 48Kb ram, CEGMON, 16KB Hires.

dave
Site Admin
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Re: FPGA Implementations

Post by dave » Mon Jul 10, 2017 3:06 pm

Looks awesome. I love the Hires mod.

Dave

Steve Gray
Posts: 193
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Location: Markham, Ontario, Canada
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Re: FPGA Implementations

Post by Steve Gray » Mon Jul 10, 2017 5:09 pm

Cool!
C4P+D&N floppy not working, 2x C4P not working, C1P not working, Superboard not working.
505 board, 610 board, Mittendorf board, TOSIE hacker board need testing, PicoDOS disk untested

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