Did some simple loopback tests of the 6850 this evening.
Was also able to load/save some programs via a USB<=>TTL cable to the PC.
Looks like both the 6850 and 6821 from Jonathan Kent are working ok in the design.
I wouldn't mind a bit of input here on what people would prefer to see first
I'll probably implement them all as time permits, since they all have benefits.
1. Interface to a real disk drive.
Pros: read/write real disks, compatibility with real OSI machines
Cons: requires some minor construction work. Simple adapter from the DE0_CV GPIO port to the disk drive via a level translator and a ULN2003 to drive the outputs. Needs some "fancy" coding for the data separator.
2. Interface to a Non-Volatile SRAM.
Pros: Allows read/write of disk images, data stays intact when machine powered off. Relatively easy to read the NVSRAM with a device programmer for loading/saving disk images. Coding relatively easy
Cons: Minor construction required. Again, GPIO port to a 40pin DIP socket.
3. Emulate the disk within the block RAM of the Cyclone V FPGA itself.
With the current design, there is enough free RAM in the FPGA itself to hold 2
x 40-track 5.25" disk images of 92160 bytes each.
Pros: Requires no construction work/modifications. Runs on a DE0_CV out of the box.
When tethered to a PC running Quartus II, it's possible to read/write the memory using the "In-system memory content editor" tool. This makes loading/saving disk images very easy indeed. Coding relatively easy.
(The disk dump utilities in "OSITOOLS.ZIP" could also be used to send a disk image back up the USB<=>TTL cable to a PC)
Cons: There isn't enough block RAM to emulate an 8" disk in the FPGA.
Disk images need to be loaded/saved at power-up, shut-down. (No worse than inserting/removing a real floppy though
Relying on the Q2 Memory tool makes the design less transportable to other platforms.
Is anyone else (apart from Jim) keen to actually take the plunge and use this project?