610 Board's RX - CLK/Data circuit - Incorrect Resistor?

[blkrckz28]

Hello All...

I have a 610 board which I am going through the calibration steps for the TX and RX (data/clk) timing adjustment via R9, R10, R18 and R19 pots.
This is for a 5 1/4" floppy drive.

The TX Data and TX Clock were fine. No issues.
The RX Clock calibration is good as well.

However, adjusting R19 to set the RX DATA negative pulse width to 6us, does nothing.
In fact, the pulse width doesn't change through the whole range of the pot R19. It sits around 8us whilst adjusting R19.

Just as a sanity check, I calculated the one-shot pulse width time based on the min/max Rext and Cext from the 610 schematic, and there is no way that these component values can reach 6us.

So, I did some research on other OSI floppy I/F boards and everything I could find had the same values for the Rext and Cext to achieve the 6us pulse width.

To achieve the 6us pulse width:
Rext should be 13K ohms (R19+R20)
If I set R20 = 8.2K and R19 = 10K, then I can dial in the 6us pulse width.

So, my questions are:
1) Does anyone have the 'actual' value for R20?
2) Is the RX DATA pulse width calibration suppose to be 6us? or something else.

Thanks
Andy

[Thomas]

The clock from the disk data separator (125KHz) creates every 8usec a RxClk on the 6850 ACIA.
At the rising edge of RxClk, the RxData line is latched into the serial shift register.
In case a data bit was present between the floppy clock signals (@ 4usec), the data bit is expanded by the U70 (pin 2,4) by about 6usec to overlap the next RxClk rising edge.
If it is expanded to 12usec or more, U70 will be still showing the last data bit at the following RxClk and cause an data error. The best pulse width is in the middle between maybe 5 and 10usec, so min 6 to max 8usec.

In case the pulse width is too long, better check/change the capacitor.