My Klyball 600D build

[ronin47]

Well that's great that you have it working!

I wonder if it was the speed or drive current (or both) that fixed it? Perhaps it's a side effect of using 100ns RAM?
Hopefully this will help someone in the future that runs into a similar problem.
Good Job!

Yeah, difficult to know, but definitely a bit odd.

I've ordered some 7404s to see if they make yet another difference, but very happy to have got here.

Hopefully this will help someone else, seems like there are a few pitfalls building these replicas.

I will make a note of all the issues I've hit along the way for others to see too.

Next I need to try and test loading and saving, see how that goes.

I've just had some new 6850s delivered so I'll pop one in in place of the recovered item I'm using at the moment.

[ronin47]

So here is the list of things that caused me problems during my build.

Everybody will be different, and I'm happy to say I didn't have any shorts at all, but what I did have were some errors of my own making, and some that were baked in to the info I had in front of me.

1. Clock circuit problem 1 - I used a 74LS92 for U29. This is what the BoM said, though the schematic said it was a 74LS93. I followed the BoM. Fixed by using a 74LS93
2. Clock circuit problem 2 - I had inserted a 150nF cap at C65, it should have been 150pF and it was effectively filtering the clock signal.
3. Video circuit - I had a placement diagram that showed 3 holes for the position of C8, with the middle pin indicated, so I connected the right and middle pins. This is incorrect and should have been the left and right pins, ignoring the middle marked pin. This led to 15Khz on the vertical sync instead of 60Hz and a rolling image.
4. Fuzzy video - this was an odd one, but ultimately turned out to be the use of a 74LS04 at U21. I swapped for a 74S04 and the fuzziness went away, so clearly some sort of timing issue. This is a bit of a gotcha as the BoM and schematic agree it should be an LS part.
5. Initial memory location - My misinterpretation, but the 2 RAM chips used for initial testing need to go into sockets U31 & U45, not U38 & U52.
6. Shift lock - There are 3 apparent connections for the shift lock switch. The middle connection is irrelevant and the switch needs to connect the left and right pins only for shift lock to function correctly.

I think that's about it so far, but if I hit any more issues going forwards I'll extend this list.

Hopefully it may help others with issues doing this build.

[ronin47]

I've been looking at cassette saving for the OSI today for fun ( ) and have hit another issue, possibly another dead IC, and though the TL866 says otherwise, I have ordered a replacement just in case. I also managed to find some 7476's as well so those are also on the way.

It would be nice if I actually had the IC's I need in stock, but like with capacitors, it's just never the case

When I run the 'SAVE' command (It's a weird and wonderful way to save, but that's another story) I can see the data leaving the 6850 and getting to where it should do in the last IC in line, U64, a 74LS76.

However, it should then output from pin 15 to the other gates, but I just see a constant square wave...

I don't have any shorts, but what's coming out of pin 15 should represent what is going into pins 2,4 & 16, and it just isn't. I did also remove the IC but there was nothing on pin 15 coming externally, so it has to be coming from the IC. So I lifted pin 15 and it's definitely being generated in the LS76.

The BoM says SNC5476J, 7476 and 74LS76, so it's looking like another possible timing issue due to a modern chip.

I probably won't use cassette much, but I want as much working before I start off on the 610 expansion board.

[Mark]

I built a KCS interface base on the OSI schematics for the 430B board Although the OSI schematics specify a 7476, I used a 74LS76 without issue. I wouldn't expect any timing issues for that circuit -- a logic controlled /2 or /4 circuit. The OSI build instructions have more details in that manual that may help.

There is some code to use to try the two different outputs from the cassette tone generation circuit here:
viewtopic.php?p=5400#p5400

I guess it could just be a bad flip flop...

[ronin47]

I built a KCS interface base on the OSI schematics for the 430B board Although the OSI schematics specify a 7476, I used a 74LS76 without issue. I wouldn't expect any timing issues for that circuit -- a logic controlled /2 or /4 circuit. The OSI build instructions have more details in that manual that may help.

There is some code to use to try the two different outputs from the cassette tone generation circuit here:
viewtopic.php?p=5400#p5400

I guess it could just be a bad flip flop...

Thanks Mark, I'll take a look.

It's possible that the LS is marginal despite testing OK, but the cassette signal never leaves it despite arriving OK.

[ronin47]

Just as a quick follow up to the fuzzy video problem, I received some 7404s this morning, and dropping one in in place of the 74S04 seems to have improved things slightly again.

So it does make me wonder if improvements in LS production techniques and having faster RAM have led to timing issues in my build.

I suppose it could equally be marginal IC's, I'll probably never know, but as long as it runs, I'm good with it.

[ronin47]

I built a KCS interface base on the OSI schematics for the 430B board Although the OSI schematics specify a 7476, I used a 74LS76 without issue. I wouldn't expect any timing issues for that circuit -- a logic controlled /2 or /4 circuit. The OSI build instructions have more details in that manual that may help.

There is some code to use to try the two different outputs from the cassette tone generation circuit here:
viewtopic.php?p=5400#p5400

I guess it could just be a bad flip flop...

Hmm, interesting, I had a look at that link and I see 2.4Khz at pin 15 of the LS76 even if I'm not saving anything. Of course that feeds pins 9 & 12, and I see it there too, and at the output on pin 11 I just see 1.2Khz.

I can see the 6850 input at pins 2,4 & 16, they look just fine when I'm in SAVE mode and do a LIST. I just see no change at pin 15 where I'd expect it.

The poke didn't work for me BTW.

We'll see what happens when the replacements arrive.

[ronin47]

OK so I still have an issue of no audio out.

What I know so far is as follows:

U64 pins 2,4 and 16 are receiving the data that is to be saved to cassette as expected. This matches what's coming from the 6850 pin 6.
U64 pins 1 & 6 are getting a clock signal of 4.8Khz
U64 pin 15 is outputting a signal of 2.4Khz. This is also seen at pins 9&12.
U64 pin 11 is outputting a signal of 1.2Khz, however it is unaffected by the signals coming into pins 2,4 & 6. Also, I do not see any signal at J2 pin 7. According to the service manual I should see a waveform here, but I don't, neither do I see one at

U69 pin 1 & pin 4 have a signal that is present during a save which looks similar to the save data from the 6850, and these stop when the save stops. (I am using the test program from the SAMs service manual that print's U repeatedly in save mode)

R50 and C12 are correct as is R86, R56, R55, R54 and C13. R57 seems to work fine,

Looking at the datasheets for U64 & U65, the only thing I can say is that CLR is held high all the time across both IC's (R86 does this), and they are active low. Should they ever go low? Not sure, bit of a head scratcher.

Also, it looks to me as though U66 is only used during program loads. Is that the case? The audio out circuit looks very simple, and does not seem to include the CA3130, or have I missed something?

[Mark]

So I checked this on my KCS board.
When there is no activity on the serial line (idle state after reset), the 7476 (U64) inputs at pins 2,4,16 are low. Pin 15 is high, and the output on pin 11 is 2400hz - this makes the 2nd half of the 7476 a divide by 2.

After I poke 64512,241 on my C4P the input pins 2,4,16 are high, pin 15 is 2400Hz and the output at pin 11 is 1200Hz - pin 15 going low blocks toggling half of every clock pulse making the output at pin 11 a divide by 4.

For a 600 board, the poke would be 61440,241 which sets a serial BREAK condition.

After looking at the datasheet for 7476, I thought the difference could be a 7476 vs 7476A since the clocks trigger slightly differently, but swapping a 74LS76A into my KCS board showed no difference.
Since pins 3,7,8 are inputs and are pulled high, I wouldn't expect any activity on those pins.

Output tone generation only depends on the 4800hz clock, serial data, and U64

CA3130 (U66) is only used for input, as are U69, U63 etc.

Why is U64 part 1 not responding to TxData input correctly? Bad IC? Is the signal at pin 4 OK?

[ronin47]

So I checked this on my KCS board.
When there is no activity on the serial line (idle state after reset), the 7476 (U64) inputs at pins 2,4,16 are low. Pin 15 is high, and the output on pin 11 is 2400hz - this makes the 2nd half of the 7476 a divide by 2.

After I poke 64512,241 on my C4P the input pins 2,4,16 are high, pin 15 is 2400Hz and the output at pin 11 is 1200Hz - pin 15 going low blocks toggling half of every clock pulse making the output at pin 11 a divide by 4.

For a 600 board, the poke would be 61440,241 which sets a serial BREAK condition.

After looking at the datasheet for 7476, I thought the difference could be a 7476 vs 7476A since the clocks trigger slightly differently, but swapping a 74LS76A into my KCS board showed no difference.
Since pins 3,7,8 are inputs and are pulled high, I wouldn't expect any activity on those pins.

Output tone generation only depends on the 4800hz clock, serial data, and U64

CA3130 (U66) is only used for input, as are U69, U63 etc.

Why is U64 part 1 not responding to TxData input correctly? Bad IC? Is the signal at pin 4 OK?

Mark, I have to say thanks for this information, it's allowed me to get the cassette save side of things working!

So I went back and double checked and noticed something I'd missed earlier. Pins 2,4 & 16 of U64 were not starting out low, but actually at about 4v. Everything else was as it should be at U64.

So I checked the output of the 6850 on pin 6, that was high as was the input to U18, pin 13. However the output from U18, pin 12, which should have been low having gone through the inverter, was actually 4v and when I ran POKE 61440,241, it went up to 5v.

This was reflected at pins 2,4 & 16 of U64.

I swapped out U18 for a replacement, and U18 pin 12 now correctly reflected what was happening at the 6850, being low at idle, as were 2,4 &16 at U64.

I tested the 74LS04 that came from U18 and it was dead. So the low on the bad U18 was 4v and the high was 5v, meaning there was never a proper transition between low and high, so although the data pulses were seen at 2,4 & 16 of U64, they were always high.

Now if I hook up to pin 9 or 7 of J2 and feed them into my speakers, I get an actual output when I save

Next I need to test the cassette input and see if that works now that I can save.