Boards for sale

[dave]

For JLCPCB, you can also just add a note that there are no solder masks. They just want to know that you didn't forget them.

[blkrckz28]

That's a really clever idea..

One of the things I want to do for the Superboard II is modify the video for 40x24. Almost all of the circuits I have seen start with the REVD board. I have a superboard II REVB, that had the video mod (40x24) back in 1980 I believe. And it is a bit unstable. The mod apparently used the rising + falling edge of the Phase-2 clock which is not symmetric, causing jitter in the pixel clock generator...

[bxdanny]

40 x 24? That is certainly a unique configuration for an OSI. The original model of the Commodore PET 2001 did do 40 x 25 video without a CRT controller chip, though later revisions used one. But it seems like the circuitry would have to be a lot more complicated than the standard SB II in order to start a line of characters 40 bytes after the previous one, rather than 32 or 64. Am I wrong? Anyway, 24 character rows of 8 scan lines each is 192 scan lines, so you would have to have had some blank lines above and below the displayed characters. How many scan lines total?

[blkrckz28]

I'll have to power it up and try how many chars per line.. I might be wrong here (I have been looking at the 50x30 and 64x32 mods, but these only apply to the rev D boards. I have a rev B, and may be mixing numbers here)

Yes, it was overly complicated and used 2 - 74123's triggered on the phase 2 clock riding/falling edges to create a 2x pixel clock pixel clock (plus a handful of discrete logic gates). There was a bunch of existing circuitry and counter mods (which calculate how many pixels per line, lines per frame) to get it to work, along with a prom change... So many cuts and jumpers.
Because the phase-2 clock's duty cycle was non-symmetric, the resulting pixel clock periods between edges was all over the place. This caused all kind of jitter between pixels. Visually on an old CRT it wasn't terrible, but on a modern 10" LCD display with composite video input, it looked terrible...

I even build an adaptor board using the AD725 (Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port) that plugs into U70 (which combines pixel data, Vsync,Hsync) to generate a cleaner composite output, but it didn't work any better than the original 7403 nand gate implementation. The stability of the pixel data and syncs were not good, and the AD725 just made that visually look worse..

I never received a document on exactly what this company did for the mod... I drew out the best I could on the orig schematics, and it didn't match any published mods that I could find. The real issues are: 1) None of the published software would work with this configuration since all the older software required the lower res configuration, and 2) the stability of the pixel clock was terrible because of the non-symetry of the phase-2 clock high/low duty cycle and 74123 stability.

I was thinking about undoing all the mods, going back to the orig implementation, but the board would look like crap when I was done because of all of the previous work that was done...

That is why I am just going to keep the original board unchanged, and build up one of the reproduces rev D boards, and just start from scratch... :-/