My Klyball 600D build

[ronin47]

Hi, I have recently built up the same reproduction PCB and have a couple of suggestions, your major issue at present does seem to relate to the clock signal though.

The circuit diagram included in the scan of the build instructions is a bit fuzzy so I also referred to a nice copy of the Rev. D schematic available from this site:

http://osi.marks-lab.com/boards/schematics/OSI600.pdf

The board should boot up with just 1kB of RAM (plus 1k video RAM) but they need to be installed into the pair of sockets nearest the edge of the PCB, in positions U31 and U45. If that does succeed the number of RAM bytes free should be 255.

Yes, there should be a good TTL level 0.98MHz clock signal at the CPU pin 37 which does come from U29 pin 11 but U29 should be a 7493 rather than a 7492. I seem to have made a similar error when I originally ordered ICs for the build, receiving a 7492 then realising the circuit called for a 7493 instead. Maybe somewhere in the documentation there is a typo, I can't recall why I originally ordered the 7492 as it is a divide by 12 counter rather than binary, divide by 16 so does not appear to be interchangeable.

Your clock signal levels at U58 do seem too low, are you seeing any signal at the output pin 8 of the 7486 U79 or input pin 1 of U29?

The link which is shown on the circuit diagram next to U29 is already connected in the default position within the PCB track layout and doesn't need to be changed or any wire link added in order to work.

Hope that helps, regards John

Thanks so much for taking the time to write back.

I did theorise that the 'wire link' was already baked into the PCB, but thanks for confirming.

I just had a look at the schematic in the assembly instructions, and the one you linked to (Way clearer, thanks) and they state that U29 is '93', which you could easily interpret as '74LS93', however the BoM states 74LS92, so it isn't really a surprise that we both ordered a 92.

I personally went with the BoM because the schematic looked like somebody drew it on wet blotting paper with a felt tip pen!!!

In addition, the service manual also shows a 74LS92 at U29, further reinforcing the error.

I have ordered some LS93's this morning and we'll see what happens once I change it.

I haven't checked U79, but will do so as soon as I have the chance, but the input of U29 is good, with a clean 4v P2P signal. Not sure why the signal at U58 is low, but if it's OK elsewhere, then I'm less worried.

You also mention the U58 being a 7400, though the BoM specifies a 74LS00 as an alternative. Given there are 'inaccuracies' in the BoM I've ordered some 7400's as well.

Once again, thanks for the help and I'll post back here when the parts have arrived and I've tested.

The rest of my RAM should be here Monday too hopefully.

[jbtech]

Hi again, if you have a clock signal with correct level at the input pin 1 of U29 that is good news.

U29 is also listed as a 74LS93 in the kit build instructions, that's probably why I didn't go with my originally ordered 74LS92 which probably was taken from the BOM. The pinout shown on the circuit diagram also matches the 74LS93 and not the 92.

I standardised on 74LS components throughout and they all seem to work fine together, with the possible exception of the video output IC U70. I fitted a 74LS03 there instead of the specified 7403 and did find the video output level was a bit lacking when used with a 75 Ohm terminated colour monitor composite video input. A 7403 may perform better having a higher output current rating or alternatively a 74S03 could also be a better choice than the 74LS03 in that position.

[ronin47]

I appreciate the tips here.

I just looked at the assembly instructions I have, and it says LS93 on the chip layout diagram, on the schematic and in the IC installation instructions, so it is just the BoM that is incorrect.

I know why it went wrong for me, because I had a modern picture of the board layout showing IC locations, I was cross referencing the BoM with the picture I had.

I had, up to the point of inserting the ICs, followed the guide 100% for the sockets, resistors, diodes etc, but then skipped to the BoM/Picture for the IC's, so I followed the BoM.

It's a small gotcha that anybody building one needs to keep an eye open for.

I did go for LS as far as possible, I think the only place I didn't was the 7408, but I may change that later.

I'll see how it goes with the video and change to a 7403 if it's not looking good, thanks. Assuming of course it works with a 74LS93 installed

[ronin47]

Annoyingly my LS93 isn't here yet, though I now have all my RAM ICs, but I'll leave them out until such time as I've been able to test the board properly with the LS93 fitted.

My shift lock is looking good though

PXL_20240122_111549247.jpg (2.43 MiB) Viewed 1754 times

[ronin47]

Well, the ICs and a bunch of others arrived. And it's better, but it still isn't booting.

I have 1Mhz at pin 37, PHI 0, and both PHI 1 & 2 are both showing clocks out. All good.

The video output shows 15.63Khz, but there is nothing on screen.

PXL_20240125_120304933~2.jpg (269.66 KiB) Viewed 1376 times

/RESET at the CPU is going high.

It's progress as at least there are clocks now.

One thing, I am using 28C16 ROMS based on an image of a completed machine, are these correct? Do the ROM files need to be byteswapped before burning to RAM?


Any Ideas would be helpful thanks.

[bxdanny]

If the CPU were jsut not running, you should see random characters on the screen. If you see NOTHING on the screen, it's probably a problem with the video circuitry. The CPU may be running fine,

[ronin47]

If the CPU were jsut not running, you should see random characters on the screen. If you see NOTHING on the screen, it's probably a problem with the video circuitry. The CPU may be running fine,

I think you may be right, I don't see anything at all and when I hit break I see activity where I expect on thing like chip select lines, address and data buses etc, but just nothing on screen, so I will focus on the video subsystem next.

[bxdanny]

You can check if the CPU is actually executing the ROM code properly by hitting <Break>C<return><return> and then SAVE<return>, looking at the signal on the TxData output of the ACIA as you hit that last return. If things are actually running correctly, you should see almost one full second of activity on that line as the ACIA outputs the message <cr><lf>OK<cr><lf> at 300 bps, with 10 NUL characters inserted after each <cr>.

[ronin47]

You can check if the CPU is actually executing the ROM code properly by hitting <Break>C<return><return> and then SAVE<return>, looking at the signal on the TxData output of the ACIA as you hit that last return. If things are actually running correctly, you should see almost one full second of activity on that line as the ACIA outputs the message <cr><lf>OK<cr><lf> at 300 bps, with 10 NUL characters inserted after each <cr>.

Thanks I will definitely try that. Looking at the 6850 on the schematic, TX Data looks to be pin 6, is that the one you mean?

[bxdanny]

Yeah, that would be it.

On the 600D, you have to hold <Break> down for bit for it to work, possibly two seconds or so.