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Ok I got some traction, I dialed it back to 1mhz got rid of the noise byte. is this the correct format 8e1 = 80, 00, tk#(delay) 8n1 = 1 byte sector header ,E000 data , 2 byte checksum or is the track header 4 bytes 80,00,tk#,start byte I wrote up to track 9 and I now get .....DEV B Not Ready it seem...

@bxdanny I have a Couple questions: should track 0 be written standard, as you don't need to fit in the extra data, plus there is no real way to reset the 8e1 before the boot. have you had any success making a disk. My progress so far write track 0 standard seems to start then looks for next track w...

I have had some success with the disk dump program. I played with the delay timing here: RDTRK4 LDA DISK+2 ORA #$80 STA DISK+2 ; UNLOAD DISK HEAD CLC RTS ; DELAY 1.25MS PER LOOP DELAY LDY #$C7 ; WAS F8 DELAY1 DEY BNE DELAY1 EOR $FF,X DEX BNE DELAY RTS I actually wanted to cut it in half with 7C but ...

Hi ,
I would like to try and burn up a disk but am not sure of the format of the first few tracks before it gets to the

80 00 07 1f
80 00 08 1f

do you leave in all the 00?

Thanks

Time to get back to this problem.
I have confirmed using the exam command dumps a good read of the track to memory, so I guess writing a utility that uses the os calls might be the way to go.
I have played around with redoing the read program with limited success. Ideas?

Well, after finding a bad 7410 I now have the clock circuit working properly switching from 1 to 2 Mhz. But after the fix I was back to no z-80 so I determined it was not the clock, both the 6502 and 6800 seemed to be working properly so I concentrated on the z-80 circuits. i could not find anything...

I finally tracked down the problem to the clock circuit, it seems the z-80 does not like to run at 1mhz which is the clock speed of the board, the schematic has a table showing the z-80 should be running at 2mhz all the time and you should be able to switch the 6502 between 1mhz and 2 MHz but its no...

Well that answers that question, So my problem must be some were else, I will check and see if somehow the data is getting overwritten when the processor is switched. I had just assumed that it was , when I reset and checked the memory it was changed. I will boot from the c3 utilities disk into 65D ...

I have a interesting memory problem that came to light trying to run cp/m, at first I thought the disk was bad but this is not the case. I dumped the first track and dissembled the first little bit, It seems osi cp/m loads some code starting at at $D000 so you need memory at $D000-$EFFF, no problem ...

This is great, I'm on holidays for a couple weeks but will try to get it going on my 510 when I return