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Hi,

I'm following the projects for memory expansions, and I have some general questions about attaching memory or peripherals to the expansion socket on the 600 board. My quotes are referring to the 600revB manual.

First of all, I found the description of the DD signal in the 600revB manual. On page D-3 in the section about the 48-line bus it says:

"B4 - DD (data direction) When pulled low by the system board, it changes the direction of the 8T26 buffers on the CPU board, and thus switches the processor from outputting data to the bus to listening to the bus."

I would like to understand the relationship of the DD signal to the R/W signal. When the CPU wants to read from a peripheral, it sets the R/W line to high. The peripheral in response sets the DD signal to low to switch the data direction of the data bus buffers. Doesn't that mean the DD is just R/W inverted, and that it isn't really necessary to have the DD signal generated by the peripheral? Would it be possible to just loop back the R/W signal with an inverter to the DD signal? Are there special timing requirements for the DD signal so it can't be derived directly from the R/W signal?

The next thing is that the above quote talks about 8T26 buffers. When I look at the circuit drawings in the 600revB manual, there are only four 8T28 buffer chips (U6 and U7 next to the CPU on "sheet 1 of 13", and U24 and U25 on "sheet 8 of 13"). I compared my own board againts the chip placement drawing on 56 of the 600revB manual, and while the chipts U24 and U25 are actually there, the sockets for U6 and U7 are empty. Is it correct that for attaching anything to the expansion socket I have to supply the data bus buffers in sockets U6 and U7? And what are the correct buffer chips, 8T26 or 8T28?

Thanks
Stephan

The relationship between the DD and R/W signal is not direct.

To read (or write) from a device on the CPU (bus) side the 8T28, the DD signal will remain high at all times. However, to read from a device on the expansion (receiver/transmitter) side of the 8T28 the DD line must be driven low when the W/R line is high. So, you need to detect when the address bus is addressing a device on the other side of the 8T28.

As to whether it should be an 8T28s or 8T26s your quote discusses the 48pin bus, which is not normally used with the 600 board directly. However there is a board available to attach the 600 to the 48pin buss via the 610 memory/disk expansion board. This is the 620 board which connects to the 610 board. It does indeed use 8T26 chips. But so does every other board that goes on the 48pin backplane.

The hierarchy is like this:
600 <-> 610 <-> 620 <-> 48pin bus

However, on the 600 board U6 and U7 need to be 8T28s as they are none inverting.

The 8T26 inverts the data that travels across it. If the devices on the expansion connector side of the 600 board were just memory, it would not make a difference. The data would be stored inverted when written, but it would be corrected when read. However, if other devices are to be used (like the floppy disk controller on the 610 board) then the data cannot be inverted across the buffers.

Hope this helps.

BillO wrote:The relationship between the DD and R/W signal is not direct.

To read (or write) from a device on the CPU (bus) side the 8T28, the DD signal will remain high at all times. However, to read from a device on the expansion (receiver/transmitter) side of the 8T28 the DD line must be driven low when the W/R line is high. So, you need to detect when the address bus is addressing a device on the other side of the 8T28.

I see, I was overlooking that the looped back DD would interfere when the address is not in the range of the peripheral on the expansion socket.

BillO wrote:As to whether it should be an 8T28s or 8T26s your quote discusses the 48pin bus, which is not normally used with the 600 board directly. However there is a board available to attach the 600 to the 48pin buss via the 610 memory/disk expansion board. This is the 620 board which connects to the 610 board. It does indeed use 8T26 chips. But so does every other board that goes on the 48pin backplane.

The hierarchy is like this:
600 <-> 610 <-> 620 <-> 48pin bus

However, on the 600 board U6 and U7 need to be 8T28s as they are none inverting.

Great, I'm already waiting for some 8T28 chips that I ordered, and I'm glad that I ordered the right ones...

BillO wrote:The 8T26 inverts the data that travels across it. If the devices on the expansion connector side of the 600 board were just memory, it would not make a difference. The data would be stored inverted when written, but it would be corrected when read. However, if other devices are to be used (like the floppy disk controller on the 610 board) then the data cannot be inverted across the buffers.

Hope this helps.

This helps a lot, thank you very much.