New data separator and motor control card

[nama]

With some proding from dave, I gave myself a crash course in Cadsoft's Eagle software.
I was surprised how simple it was to learn the basics.

I have completed a first pass of the floppy data seperator and motor control card schematic.
I'm still learning so please forgive me as I think it's a little rough in places, and I believe that some of the selection of parts may be a little off. Strangely enough I couldn't find a 74LS38 in the Eagle parts list so for now I have used a 74LS37 instead.
You can download the Eagle files in at:

https://public.me.com/lord_philip

Look under the Ohio Scientific folder.
Presently I'm calling the file alpha0.1.

Cheers
Philip

[dave]

Hi Philip,

You learned your way around eagle quickly! One thing you should do is run the ERC (electrical rules check) on the schematic. It will be very informative. For one thing, it will point out that the various chips automatically connect their power pins to VCC and GND. The cleanest way to do this is to name the 5V net as "VCC".

The reason the 74LS38 was used in the original schematic is that it is an open-collector buffer, meaning that unlike the 74LS37, which you have in the circuit, it has an open collector output rather than a totem-pole output, and multiple outputs can be connected together. The chips differs from the open-collector 74LS01 in that it is a buffer, designed to sink a greater current, 48 mA compared with the 18mA of the 74LS01. So you probably want to substitute the 74LS38 for the 74LS37. For an open collector output, it's OK to ground the output directly, since the only current path to VCC is through a pullup. That would not be true for a regular TTL or LS-TTL output.

A useful convention is to name the nets coming in / going to the connectors according to their function, and then attach net labels, displaying the labels near the connector, so someone reading the schematic can tell what connects to what. Usually the connectors offer the option of including a rectangular block with all the connectors, as you have chosen in the schematic, as well as an option to place the pins individually. Sometimes the second option allows you to organize the schematic in a way that is easier to follow, and allows more room for labeling. To some extent, that is all a matter of taste.

A typical convention is to put the inputs on the left side of the page, and outputs on the right side, so the logic flow left to right. An alternative, similar to your layout, is to place the host (computer board) on the left, and the peripheral (floppy) on the right.

I think that most of the capacitors will be available in 0.1" ceramic form factor, which will save board space.

Regarding the switches, it would probably be just as useful and take less space to use jumpers for these as well. A couple of 3-pin jumpers can emulate a DPDT switch, and you can place the jumpers close to the circuitry, simplifying layout if space is tight. These are all settings that won't be changed during normal operation.

I think the whole layout can fit in a 3x4" board size. I'd position the Molex connectors 2" from one edge, and 1" from the other, so that the paddle board will fit inside a standard case when mounted on the 505 or 470 card (or 610 card for that matter.)

I haven't yet had a chance to follow all the wiring. Labeling the nets at the connectors will help avoid mistakes. I see you are have a switch to choose between the floppy READY signal, +5V, or GND on pins 21 and 24 of the 505 card. I haven't yet checked this out.

This week, I'm racing to get a layout done on my current project for work, but when I'm done, I will be happy to spend some time going through the schematic and helping out with the layout.

Best regards,

Dave

[nama]

Hi Dave,
Thanks for the reply.

Yes, I was pleasantly surprised how easy Eagle was to learn. Obviously I only know the basic stuff it present, but that was enough to put this board (mostly) together.

Strangely enough I could not find a 74LS38 in the parts library, thats why I chose the 74LS37 thinking it was basically the same...seems I was wrong. I agree that changing the switches to jumpers and using smaller capacitors would be a good idea to save space.

I used a switch to jumper pins 21 and 24 to either the READY signal or GND. The Peek65 article says:

"Note, if you have a drive with the READY signal you can connect this line to pins 22(???) and 24 of the OSI controller, otherwise these pins should be grounded."

So I made it switchable. One thing to mention here is that in the text of the article it says Pin 22, but in 'Table 2' (OSI CONTROLLER - DISK DRIVE CONNECTIONS AHD FUNCTIONS) from the same article it shows Pin 21...I made an educated guess and used Pin 21 and assumed the writeup was incorrect. I could be wrong.

I ran ERC over the layout, and yes indeed there are a few issues. I think the best thing to do now is to wait until you have some free time so you can wave your magic wand over the entire schematic and board design and get it in a functional state. I can then look over your fixed layout and see what has changed and learn how to do things properly. I'll continue to play with Eagle and see what else I can learn, but I'll probably do my learning on another project for the time being.

Cheers

Philip

[dave]

I will check it out more thoroughly probably in a week or so. The other thing to consider is that there are two standard drive pinouts--the Shugart standard, and the PC standard. They are similar, but several pins are different. It may be worth thinking about how both can be supported, since the PC format seems to be more common in newer 3.5" drives.

Dave

[nama]

I hadn't even realize that they were not the same. The schematic is presently drawn for the Shugart drive, and certainly we also need compatibility with PC drive too.

After a little research, it seems that the following pins are different between Shugart and PC drives:

SHUGART DRIVE
2 = /DCD - Disk Change Detect
4 = /DS3 - Device Select 3
6 = /INUSE - A common open-collector LED driver signal.
10 = /DS0 - Device Select 0
12 = /DS1 - Device Select 1
14 = /DS2 - Device Select 2
16 = /MTRON - Motor On
34 = /RDY - Drive Ready

PC DRIVE
2 = /REDWC - Density Select
4 = n/c - Reserved
6 = n/c - Reserved
10 = /MOTEA - Motor Enable A
12 = /DRVSB - Drive Sel B
14 = /DRVSA - Drive Sel A
16 = /MOTEB - Motor Enable B
34 = /DSKCHG - Disk Change

Pins 2, 4 , 6 and 14 are not actually connected on the present schematic, Obviously the Shugart drive doesn't need them to work, but I don't know if the PC drive needs these connected or not. Pins 4 and 6 on the PC are not connected anyway, so we can ignore these. So that leaves Pins 2, 10, 12, 14, 16, and 34.

I hope you have a better idea than I as to what is needed to get our design to work with both type of drives.

Phil

[nama]

Just another quick update.
I found this site:

http://home.iae.nl/users/pb0aia/cm/8-525.html

It covers converting devices that use 8" drives to 3.5" drives. As far as I can tell, a Shugart 50 pin connector carries basically the same signals as a Shugart 34 pin connector (albeit with different pin locations) so I think what is discussed here applies to what we need to do.

Having read through this page I think we have 3 issues with making sure PC 3.5" drives are supported. Please correct me if I am wrong.

- Most PC disk drives do not provide a READY signal but send a DISK CHANGE signal on line 34 of the interface.
- Motor enable Pin 16 constant motor on issue. I'm assuming this is also solved for PC 3.5" drives with the use of our motor control circuit.
- Pin 2 may need to be configured for what particular density drives used. 0V (signal active) sets HD and inactive sets low density (SD/DD, or FM/MFM). Normally it's not fitted, so active (low) sets low density and inactive (or open-circuit) sets high density

So, unless I am mistaken the only pins we need to worry about are pins 2 and 34. Pin 2 could be selected by using a jumper to pull it high or low, if this is actually needed at all.
The Peek65 articles solution to pin 34 is to just short the drive ready lines (OSI connector pins 21 and 24) to GND when using drives that don't supply the READY signal on this pin. The only downside I can see is that the drive may actually not be in a ready state although the OSI machine will think it is. In actual real world terms I'm not sure if this is an issue.

Anyway, you probably know this stuff already, but for me it was interesting finding out.

[nama]

Thanks to Steve Gray who had a look at my alpha 0.1 files, he was able to play around with the layout and get it to auto route. I took the file Steve altered and then did the following:

- Manually routed GND trace with .5 thickness trace (presently only the GND is routed, all the rest can be auto routed)
- Replaced all switches with jumpers
- replaced all caps with smaller 0.1" size
- changed the trim pot to a different style
- Made sure all the ic's VCC and GND were connected to the appropriate power lines
- General tidying up and renaming of some parts (still there are two capacitors and one resistor that I can't read the rating from the Peek65 article)

The file has now been updated on my site to alpha 0.2:

https://public.me.com/lord_philip

Look under the Ohio Scientific folder.

Dave, we would appreciate if you could take a look at the latest file and fix it up where needed.

Thanks again
Philip

[dave]

Hi Philip,

That's great! Right now I am in full crunch mode trying to get a current consulting project finished, and that's in addition to my day job, so it will likely be the weekend before I have a chance to go over it properly. I have also been thinking that really, there's no need for the double-sided option, especially since the two sides aren't really seamlessly integrated into a single file system--it looks like two drives to the OS. For compatibility, there is no benefit, since all the original disks will be single sided, and even for the newer drives with two sides, we'd not be gaining anything in terms of compatibility. The wasted extra space is not a big deal, since the software will be archived on PC's.

Doing so would eliminate the need for any mods on the controller board (505, 470, or 610 board), so the paddle board could be more plug-and-play, and also might eliminate a chip or two from the design. It would also decrease the likelihood of producing disks that other OSI systems can't read.

I'm sure that there's a way to easily switch between the Shugart and PC standards. As you noted, there are only a few lines different, and probably a jumper selection could switch between the two.

The other thing I was thinking about is that with the data separator built in to the floppy cable interface, it might be possible to make another adapter board that would attach to the paddle board, and to a PC serial and parallel port, and write a program to pull data directly from a modern floppy drive to a PC, for people who have software, but don't necessarily still have a functioning OSI computer. That may aid in the software preservation effort.

Best regards,

Dave

[nama]

I'm all for making it easier for back up files for preservation, so I think your idea could be a good one. Presently I'm trying to make working backups of some old 1978 Apple II cassettes so I understand how difficult these things can be. Some of these old tapes seem too far gone for any amount of audio filtering to help.

I also like your thinking on the floppy adaptor. As you know, I personally would prefer to hack my vintage machine as little as possible, and it seems the benefits of having double side are indeed limited.

Looking forward to your next message.

Philip

[Steve Gray]

I just picked up a 610 board off ebay... no paddle board, so I'm hoping things go well with this project. The 610 board is missing all the major chips, but I managed to find some 6850's on ebay. I still need to find a 6820 and some 2114 rams.... does anyone know of a good source?

Steve