ROM-mapping jumper on 50x-series CPU boards
Posted: Wed Dec 28, 2011 4:46 pm
A short description of the ROM/EPROM page remapping scheme which allows a single 2K ROM to store 8 256-byte code blocks to configure the OSI CPUs for ROM BASIC, disk boot, ASCII vs Polled Keyboard, serial vs video-based monitors, while avoiding stepping on the serial port at FC00.
The ROM mapper is a clever circuit to work around a legacy hardware compatibility issue. The OSI 500 board had three 1702 256 byte EPROMS at FD00 (keyboard routine) FE00(65V monitor) and FF00 (system initialization, and either disk boot, or ROM BASIC support routines). He also put the cassette port at $FC00, and a PIA at $F700. The philosophy here was to put the ROM and memory mapped I/O as high as possible, to leave the largest possible contiguous space free from 0000 up.
When Mike Cheiky went to the 2K ROM for the later 500/502/505 boards, he needed to keep compatibility with the existing board, in order to be able to use the same code across the line. Otherwise, he would have just put the ROM at the top of memory, from F800 to FFFF, just like on the Superboard II. To emulate the previous scheme of 3 256K ROMS, and to be able to use the same ROM for all the C2 computers, he put 8 different 256-byte code blocks in the 2K ROM, including the monitors for video (65V) and serial (65A) systems, keyboard routines supporting ASCII and polled keyboards, and system init routine with eithe disk boot code, or ROM BASIC I/O support. Here is the schematic, taken from the 502 board schematics:
The address logic decodes the address lines and provides active-low lines when the FDx, FEx, or FFxx ranges are addressed. Those are the /FDXX, /FEXX, and /FFXX lines on the schematic.
Each of those lines can be made to address any block in the ROM, through the jumper block and the 74148 8-line priority encoder. The 74148 monitors 8 lines, and output a 3-bit code corresponding to the highest asserted line. In this application only one line is asserted at a time, so asserting any input from 0-7 generates a one's complement 3-bit value 0-7 which is fed to the highest 3 address lines of the ROM. This allows any ROM segment to be mapped to FD00, for example, by tying the /FD00 select line to the encoder input for that block.
Here is a picture of an unpopulated ROM jumper block on a 505 rev B board. Note the circuit is similar to the one above, but drops the AND with 02-VMA, The jumper pinouts may be different from the 502 (I don't have mine available at the moment.)
By default, the polled keyboard routine in block 2 is mapped to FD00, so the /FD00 line is jumpered to input 6 of the '148, via the jumper block.
FE00 points to the 65V monitor for video boards, block 3, so input 4, pin 1 of the '148.
FF00, on a disk system, point to block 7, the H/D/M? code. Input 0, pin 10 of the '148.
FF00, on a ROM BASIC system, points to block 4, input 3, pin 13 of the '148.
So, if you wanted to switch back and forth between ROM BASIC and disk boot, you could wire a switch to connect /FF00 to pin 10 or 13 on the '148.
All the connections are made through the provided jumper block.
The reason that the select line is connected to 7 minus the block number (e.g., input 0 is block 7) is that the outputs are all inverted, producing the one's complement (asserting inputs 0 to 7 sequentially would count from 7 to 0 at the outputs)
The 74148 has a pair of complementary status outputs, EO and /GS. The EO output is high whenever one of the lines is selected. The original intention is to cascade multiple 74148's to build larger priority encoders. The /GS line goes low whenever a line is selected (the complement of EO). The intention of this line is to signal the logic circuit that a line has been asserted, and the encoded number at the outputs is valid to be read. This allows distinction between the '0' input assertion and no inputs asserted. Note that the E0 and /GS outputs are mostly always complementary (unless the EI input is high, then both are high. This circuit ties EI low.) Therefore, a high EO and a low /GS both indicate a line has been asserted, and either can function as chip select for the ROM, depending on whether the chip select is active high or active low. The 2316 ROM uses an active high chip select, so the EO line is used to derive the ROM chip select. On the 502 board, this is ANDed with the 02-VMA (phase 2 clock) signal (via a 3-input NAND and 7404 inverter), to ensure only valid address are mapped, deriving the chip select for the 2316.
There is a provision to substitute a 2716 for a 2316. In circuit, the difference between the 2316 ROM and the 2716 EPROM is that the 2316 has three active-high chip selects, while the 2716 has an active-low chip select, and two programming pins. For the 2316 (unmodified factory circuit), the active-high chip select is fed to the CS1 pin of the 2316. To facilitate use of a 2716, the 502 board bypasses the 7404 inverter to derive the active-low chip select from the active-high signal, and provides pads for jumper-selecting either the active low or active high chip select, and for tying pin 10 --the 2316 CS3 line, or the 2716 programming pin.--high or low.
Note that EO and /GS are always complementary if the EI input is low, as in the OSI circuit. For the 505 board, the designer realized this, and, by ANDing the address decode logic with 02-VMA prior to deriving the /FDxx, /FExx, /FFxx signals, removed the need for the extra AND operation. This allows the EO to be used as an active-high chip select (for 2316), and /GS to be used as an active low chip select (for 2716), selectable by jumper, slightly simplifying the circuit.
Hope that helps. If anyone has something to add or clarify, that would be much appreciated!
Dave
The ROM mapper is a clever circuit to work around a legacy hardware compatibility issue. The OSI 500 board had three 1702 256 byte EPROMS at FD00 (keyboard routine) FE00(65V monitor) and FF00 (system initialization, and either disk boot, or ROM BASIC support routines). He also put the cassette port at $FC00, and a PIA at $F700. The philosophy here was to put the ROM and memory mapped I/O as high as possible, to leave the largest possible contiguous space free from 0000 up.
When Mike Cheiky went to the 2K ROM for the later 500/502/505 boards, he needed to keep compatibility with the existing board, in order to be able to use the same code across the line. Otherwise, he would have just put the ROM at the top of memory, from F800 to FFFF, just like on the Superboard II. To emulate the previous scheme of 3 256K ROMS, and to be able to use the same ROM for all the C2 computers, he put 8 different 256-byte code blocks in the 2K ROM, including the monitors for video (65V) and serial (65A) systems, keyboard routines supporting ASCII and polled keyboards, and system init routine with eithe disk boot code, or ROM BASIC I/O support. Here is the schematic, taken from the 502 board schematics:
- ROM-Schematic.jpg (160.22 KiB) Viewed 4263 times
Each of those lines can be made to address any block in the ROM, through the jumper block and the 74148 8-line priority encoder. The 74148 monitors 8 lines, and output a 3-bit code corresponding to the highest asserted line. In this application only one line is asserted at a time, so asserting any input from 0-7 generates a one's complement 3-bit value 0-7 which is fed to the highest 3 address lines of the ROM. This allows any ROM segment to be mapped to FD00, for example, by tying the /FD00 select line to the encoder input for that block.
Here is a picture of an unpopulated ROM jumper block on a 505 rev B board. Note the circuit is similar to the one above, but drops the AND with 02-VMA, The jumper pinouts may be different from the 502 (I don't have mine available at the moment.)
- 505bare.jpg (414.3 KiB) Viewed 4263 times
FE00 points to the 65V monitor for video boards, block 3, so input 4, pin 1 of the '148.
FF00, on a disk system, point to block 7, the H/D/M? code. Input 0, pin 10 of the '148.
FF00, on a ROM BASIC system, points to block 4, input 3, pin 13 of the '148.
So, if you wanted to switch back and forth between ROM BASIC and disk boot, you could wire a switch to connect /FF00 to pin 10 or 13 on the '148.
All the connections are made through the provided jumper block.
The reason that the select line is connected to 7 minus the block number (e.g., input 0 is block 7) is that the outputs are all inverted, producing the one's complement (asserting inputs 0 to 7 sequentially would count from 7 to 0 at the outputs)
The 74148 has a pair of complementary status outputs, EO and /GS. The EO output is high whenever one of the lines is selected. The original intention is to cascade multiple 74148's to build larger priority encoders. The /GS line goes low whenever a line is selected (the complement of EO). The intention of this line is to signal the logic circuit that a line has been asserted, and the encoded number at the outputs is valid to be read. This allows distinction between the '0' input assertion and no inputs asserted. Note that the E0 and /GS outputs are mostly always complementary (unless the EI input is high, then both are high. This circuit ties EI low.) Therefore, a high EO and a low /GS both indicate a line has been asserted, and either can function as chip select for the ROM, depending on whether the chip select is active high or active low. The 2316 ROM uses an active high chip select, so the EO line is used to derive the ROM chip select. On the 502 board, this is ANDed with the 02-VMA (phase 2 clock) signal (via a 3-input NAND and 7404 inverter), to ensure only valid address are mapped, deriving the chip select for the 2316.
There is a provision to substitute a 2716 for a 2316. In circuit, the difference between the 2316 ROM and the 2716 EPROM is that the 2316 has three active-high chip selects, while the 2716 has an active-low chip select, and two programming pins. For the 2316 (unmodified factory circuit), the active-high chip select is fed to the CS1 pin of the 2316. To facilitate use of a 2716, the 502 board bypasses the 7404 inverter to derive the active-low chip select from the active-high signal, and provides pads for jumper-selecting either the active low or active high chip select, and for tying pin 10 --the 2316 CS3 line, or the 2716 programming pin.--high or low.
Note that EO and /GS are always complementary if the EI input is low, as in the OSI circuit. For the 505 board, the designer realized this, and, by ANDing the address decode logic with 02-VMA prior to deriving the /FDxx, /FExx, /FFxx signals, removed the need for the extra AND operation. This allows the EO to be used as an active-high chip select (for 2316), and /GS to be used as an active low chip select (for 2716), selectable by jumper, slightly simplifying the circuit.
Hope that helps. If anyone has something to add or clarify, that would be much appreciated!
Dave